By Michiel Steyaert, Arthur H.M. van Roermund, Herman Casier
Analog Circuit Design comprises the contribution of 18 tutorials of the 17th workshop on Advances in Analog Circuit layout. every one half discusses a selected to-date subject on new and priceless layout rules within the quarter of analog circuit layout. each one half is gifted via six specialists in that box and cutting-edge details is shared and overviewed. This publication is quantity 17 during this winning sequence of Analog Circuit Design.
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Extra resources for Analog circuit design : high-speed clock and data recovery, high-performance amplifiers, power management
The advantage of a digital filter implementation is that it allows realization of long time constants with small area, so that the need for large capacitors is completely avoided. However, as shown in Fig. 3, the use of a digital loop filter introduces new challenges to the phase detector and VCO. In particular, the phase detector must be altered such that it produces a reasonably high resolution digital signal that represents the phase difference between the clock and data signals. The VCO must be altered such that it changes its instantaneous frequency according to a digital signal while still maintaining low jitter generation.
A double step has been inserted in phase selection to allow working with 16 phases instead of 32 for +/− 7800 ppm maximum tracking capability at 6 Gb/s without exceeding the 750 MHz operation. At the same time, to preserve the frequency resolution in +/− 200 ppm mode, a programmable decimation has been inserted in the frequency path, periodically blanking the injection of the integrated value Ival into the cyclic accumulator. Figure 22 also shows the CDR capability to increase Kp and Ki to allow fast locking in FC applications.
15). The data eye reconstructed by the DFE is shared between the data path and the CDR path. The data path, shown in Fig. 16, makes use of a 10 ratio in demuxes, to satisfy the FC requirement for latency minimization. An overall serial to Mux input selection Latch input Latch state Eval Hold Mux input Mux output Fig. 13 Timing advantage of a latch-based DFE Mux delay 26 M. Pozzoni et al. Vdd RL FF delay RL Delay [ps] 40 35 30 25 20 15 –80 –70 –60 –50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 CK CK-DATA shift [ps] CKN Fig.
Analog circuit design : high-speed clock and data recovery, high-performance amplifiers, power management by Michiel Steyaert, Arthur H.M. van Roermund, Herman Casier